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12-bit 160 MSPS Dual TxDAC D/A Converter

Model: AD9773

  • 12-bit resolution, 160 MSPS/400 MSPS input/output data rate
  • Selectable 2×/4×/8× interpolating filter
  • Direct IF transmission is possible for 70 MHz + IFs through a novel digital mixing process
  • fS/2, fS/4, fS/8 digital quadrature modulation capability
  • User selectable twos complement/straight binary data coding
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The AD9773 is the 12-bit member of the AD977x pin-compatible, high performance, programmable 2x/4x/8x interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system-level options. These options include selectable 2x/4x/8x interpolation filters; fS/2, fS/4 or fS/8 digital quadrature modulation with image rejection, a direct IF mode, programmable channel gain and offset control, programmable internal clock divider, straight binary or twos complement data interface and a single-port or dual-port data interface.

The AD9773 features the ability to perform fS/2, fS/4 and fS/8 digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, the AD9773 accepts I and Q complex data (representing a single or multi-carrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. Another digital modulation mode (for example, the direct IF mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the DAC update rate.

  • 12-bit resolution, 160 MSPS/400 MSPS input/output data rate
  • Selectable 2×/4×/8× interpolating filter
  • Direct IF transmission is possible for 70 MHz + IFs through a novel digital mixing process
  • fS/2, fS/4, fS/8 digital quadrature modulation capability
  • User selectable twos complement/straight binary data coding
  • User programmable channel gain control over 1 dB range in 0.01dB increments
  • User programmable channel offset control ±10% over the FSR
  • Ultrahigh speed 400 MSPS DAC conversion rate
  • Internal clock divider provides data rate clock for easy interfacing
  • Flexible clock input with single-ended or differential input, CMOS or 1 V p-p LO sine wave input capability
  • 80-lead thin quad flat package and exposed pad (TQFP_EP)
 
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