The ADSP-218xN series consists of six single chip microcomputers
optimized for digital signal processing applications. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM.
ADSP-218xN series members combine the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory.
ADSP-218xN series members integrate up to 256K bytes of onchip memory configured as up to 48K words (24-bit) of program RAM, and up to 56K words (16-bit) of data RAM. Powerdown circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-218xN is available in a 100-lead LQFP package and 144-ball BGA.
Fabricated in a high-speed, low-power, 0.18?m CMOS process, ADSP-218xN series members operate with a 12.5ns instruction cycle time. Every instruction can execute in a single processor cycle.
- Single-cycle instruction execution
- Single-cycle context switch
- 3-bus architecture allows dual operand fetches in every instruction cycle
- Multifunction instructions
- Independent ALU, multiplier/accumulator, and barrel shifter computational units
- Two independent data address generators
- Powerful program sequencer provides zero overhead looping conditional instruction execution
- Programmable 16-bit interval timer with prescaler
- 100-lead LQFP and 144-ball BGA
- Six external interrupts
- 13 programmable flag pins provide flexible system signaling
- UART emulation through software SPORT reconfiguration
