ADSP-TS101S is first member of TigerSHARC processor family. Targeted at numerous signal processing applications that rely on multiple processors working together to execute computationally-intensive real-time functions, ADI’s TigerSHARC processor is well-suited to video and communication markets, including 3G cellular and broadband wireless base stations, as well as defense, medical imaging, industrial instrumentation. The ADSP-TS101S features static superscaler architecture which combines RISC, VLIW and standard DSP functionality. Native support of fixed and floating point data types, coupled with leading edge multiprocessing capabilities allows TigerSHARC processor to offer unrivaled DSP performance. At 300MHz clock rate, ADSP-TS101S offers industry’s highest 16-bit fixed-point performance and 32-bit floating 1024-point complex FFT time of 32.5 microseconds.
- Static superscalar architecture which supports 1-, 8-, 16- and 32-bit fixed point as well as floating point data processing
- High performance 300MHz, 3.3ns instruction rate DSP core
- 6MB on-chip SRAM internally organized in three banks with user-defined partitioning
- 14 channel, zero overhead DMA controller
- Enhanced communications instruction set for wireless infrastructure applications allows for TigerSHARC to offer complete base band processing
- Three internal 128-bit wide internal buses providing total memory bandwidth of 14.4Gbps
- Software radio approach allows for adoption of single platform for multiple wireless telecommunication standards
- Single instruction multiple-data (SIMD) operation supported by two computation blocks each with ALU, multiplier, shifter and 32-word register file
- Assembly and C language programmability
